The present invention relates to managing configuration space.
In many computer environments, a fast and flexible interconnect system can be desirable to provide connectivity to devices capable of high levels of data throughput.
In the fields of data transfer between devices in a computing environment PCI Express (PCI-E) can be used to provide connectivity between a host and one or more client devices or endpoints. PCI Express is becoming a de-facto I/O interconnect for servers and desktop computers. PCI Express allows physical system decoupling (CPU <-> I/O) through high-speed serial I/O. The PCI Express Base Specification 1.0 sets out behavior requirements of devices using the PCI Express interconnect standard. According to the Specification, PCI Express is a host to endpoint protocol where each endpoint connects to a host and is accessible by the host. PCI Express imposes a stringent tree structure relationship between I/O Devices and a Root Complex.
PCI device design can be engineering intensive and multiple function devices require additional effort to implement register sets per added function. Hardware needs to present a consistent model to software but aspects of a design such as the functions, devices, embedded bridges, etc., might not be determined early in the design and might need to change during development.
In order to present a model to software, traditional devices include a set of hardware presentation registers that form a presentation interface for the device to a host. The presentation registers define the capabilities of device and address space requirements for the device and thus provide a standardized mechanism for software to be able to control controllable functions of one or more devices and to access status in respect of those functions. In the present application such a presentation layer, or interface is termed a configuration space and the presentation registers are termed Configuration Space registers, or CSRs. Although these are terms known in the context of PCI and PCI Express, it is to be understood that these terms are to be interpreted in the context of the present document to include other forms of presentation space and presentation registers and is not limited to PCI and PCI Express implementations.
In a situation where there can be a potentially large number of real and/or virtual resources, not only would the large number of registers needed take up a lot of real estate on an integrated circuit, the interconnects the registers would require when implemented as flip-flops would take up a considerable area of an interconnection device and indeed can limit the available number of devices that can be supported.